Introduction to Biasing and Load Line Analysis
Biasing is a fundamental topic that keeps coming up in all areas of electronics, so let's take a "black box" approach first, to understand why biasing is necessary, whether you are using vacuum tubes, transistors, or some as-yet-undiscovered technology.
Ever since Lee De Forest (1873-1961) patented the triode valve in January 1907, electronic circuits have been able to amplify signals by controlling an output signal of greater power with an input signal, such as the weak output of a microphone. In order to do this, of course, each amplifying stage requires another input of electrical power, usually DC power, which supplies the additional power provided in the output signal. The weak input signal modulates the DC input to generate a stronger output signal. One interpretation of "biasing" is the provision of this DC input. You will sometimes hear of modules being provided with "bias" instead of a power supply. This is a simple matter to arrange, as the "bias" input is just an input that has to be provided with a power supply, e.g. 12 Volts.
However, in electronic design, we are normally more involved with the details of providing bias voltages and currents to the terminals of every active device in a circuit, and these bias points are usually all derived from one of the circuit's power supply inputs.
Let's expand the "black box" a little to see where this DC power is going:
There is an active device inside the "black box" which provides the amplifying capability. The active device has an input and an output (some active devices have more inputs and/or outputs). Usually, each input and output has to be supplied with a DC bias current or voltage. This is the job of the bias generators, which convert the DC power input into the correct bias level for each active device terminal. Bias generators are usually passive networks of resistors, but could also contain active devices themselves. The active device is also connected to the common reference ground (either directly, or through another bias generator which is not shown).
Note that this "black box" amplifier is configured as an AC signal amplifier, that is the DC level on the input will be ignored, and has no effect on the DC level at the output. The input and the output are therefore isolated by capacitors to block the DC and pass AC signals. To prevent the input and output signals being shorted out by the bias generators, an AC block is shown symbolically as an inductor (which has a high impedance to AC signals) between the bias generator and the active device terminal. This may be usual in radio frequency and microwave circuits, however at low frequencies we normally rely on a high resistance or a current-source circuit in the bias generator to avoid shorting out AC voltages on the active device terminals.
What about DC amplifiers? You obviously can't have DC bias levels interfering with the inputs and outputs, so in these cases, the active devices must be arranged so that the main bias level inputs are separated from the input and output terminals, the input signal is itself valid throughout the whole of its range as an active device DC level, and the output DC level is controlled by active devices as the desired DC output. But to simplify matters, we will consider only AC amplifiers to begin with.
Introduction to Bipolar Junction Transistor BiasingThe first step in using a bipolar junction transistor to do something useful, like amplifying a signal, is to set up the correct currents and voltages at its terminals to allow it to work properly.
The most common bias circuit for a discrete bipolar amplification stage is the emitter feedback circuit shown below.
As the bipolar transistor is a current-controlled device, the most obvious bias technique might seem to be to provide a small current at the base (b), perhaps using a resistor Rb1, but no Rb2, connecting the emitter (e) to ground, and using the output current at the collector (c) to develop an output voltage across the collector resistor Rc. The collector current and voltage needs to be set up so that the output voltage can vary by the largest possible excursion in either direction, as a first approximation this is about half the voltage Vcc. These types of amplifier stage are not usually used for large output voltage swings, as the distortion levels tend to be unacceptable, so a reasonable variation in the collector voltage is tolerable, with the output voltage swing normally being a small fraction of the collector voltage.
However, the current gain exhibited by bipolar transistors varies both from one device to another, and in the same device, most importantly, as its temperature varies. In fact if you try the bias arrangement with a single base bias resistor, you will find that you need a variable resistor to get the collector voltage right, and then it will vary significantly even if you warm the transistor merely by holding its case with your fingers.
The current gain of a 2N3904 transistor at a collector current of 1mA varies from about 150 at -40C to about 375 at 125C. Even in a benign temperature environment, the current gain variations could be up to 2:1 as a transistor warms up from self-heating, so setting the collector current by relying on a fixed base current is not acceptable.
The introduction of an emitter resistor Re is what provides this classic bias circuit with stability against transistor characteristic and temperature variations. Remember that a BJT transistor is a current-controlled device: A 2N3904, for example, has a current gain of 100 to 300 (the ratio of current into the collector to current into the base), measured at a collector current of 10mA, because it varies somewhat with collector current. The DC current gain is known as the transistor beta, or HFE = Ic/Ib. Since the base current and collector current both flow out of the common emitter terminal, Ie/Ib = beta + 1, but very often the collector and emitter currents are assumed to be the same since the difference is small. So, the ratio of the voltage drop across the collector resistor must be the same as the ratio of the collector resistor to the emitter resistor. All we have to do is fix the voltage across the emitter resistor, so that by Ohm's law, and the ratio between collector and emitter resistor, the correct collector voltage is obtained.
Fixing the emitter voltage makes use of the fact that the bipolar transistor base-emitter voltage drop (in forward bias) is normally about 0.7 V at typical temperatures and operating currents, varying from 0.4V at Ic=0.1mA and +125C, to about 1.0V at -55C and Ic=100mA, or over a range of about 0.3V between -55C and +125C, so if the voltage at the base is fixed, then the voltage at the emitter can vary by no more than about +/- 0.15V over the temperature range -55C to +125C.
Here is a quick way to simulate bipolar transistor characteristics using Linear Technology Corporation's SwitcherCAD 3 software:
Load the file curvetrace.asc, which you should find somewhere like:
C:\Program Files\LTC\SwCADIII\examples\Educational folder
To view the transistor Vbe characteristics, select Simulate/Run, and when it asks you to select visible waveforms, select V(n001) which is the base node (the emitter is grounded, so this will show Vbe).
To change the transistor type, just click on the value under "Q1"; the LTC library standard.bjt includes the 2N3904 Philips model. The plot for Vbe for collector-emitter voltage from 0 to 15V on the X axis, and base current curves for 10 to 100 microamps, is shown below:
If we set the emitter resistor voltage drop to 1.5V, then the voltage variation possible across the emitter and collector resistors caused by variations in Vbe over temperature extremes is only +/- 10%. This will be acceptable for most purposes.
Now we can apply a logical design procedure to the bias circuit as follows:
- For this example we will assume a power supply voltage of 12V, and a collector current of 10mA. If the transistor has 6V across it, the power dissipation will be 60mW. This is well within the maximum power rating of 625mW, and will allow operation (with derating for temperature) up to +125C.
- Select an emitter resistor voltage drop (1.5V, for reasons given above). Calculate the emitter resistor = 1.5/0.01 = 150 ohms
- Calculate the minimum collector voltage for linear operation, which is aproximately the same as the base voltage = 1.5 V + Vbe = 2.2V
- Calculate the mid-point (average) of the collector voltage swing = (12V + 2.2V)/2 = 7.1V
- Calculate the collector resistor = (12V-7.1V)/10mA = 490 ohms. The nearest preferred value is 510 ohms. This will give a collector voltage of 6.9V, +/- 10% over temperature extremes which is 6.2 to 7.6V. Thus, a useful voltage swing at the collector of up to about +/- 4V can be expected.
- Calculate the base voltage = 1.5 + Vbe = 2.2V
- Decide on a suitable current flow in the base voltage generating potential divider consisting of Rb1 and Rb2. We want variations in base current not to affect the base voltage too much. The base current will be between 10mA/300 and 10mA/100 i.e. 33 to 100 microamps. Any variation in base voltage ought to be less than the unavoidable Vbe variations, which we have allowed to be 10%. Assuming a 5% effect from base current variations, which are a maximum range of +/-33 microamps, a standing current of at least 33/0.05 = 670 microamps is required, which flows through Rb1 and Rb2. Rb2 has 2.2V across it, and only the standing current flows through it, therefore Rb2 = 2.2/0.67mA = 3.28 k, very close to a preferred value of 3.3k. Rb1 has (12-2.2) = 7.8V across it, and a nominal current of 0.67 + 0.067 mA, therefore Rb1 = 9.8/0.737mA = 13.3k, which rounds to a preferred value of 13k.
Exporting the SPICE netlist using the illustrated circuit file bjtbias.CCT with Circuit Scribe, and adding necessary lines for LTC SwitcherCAD to do a DC operating point analysis, we get the following SPICE input file:
* Model for LTC SwitcherCAD to check DC bias voltages .TEMP 25 V1 3 0 DC 12 .OP VIN 11 0 AC 1. * The netlist exported from Circuit Scribe: *SPICE BJT Biasing Q1 2 1 4 2N3904 Rc 3 2 510 Rb1 3 1 13k Rb2 1 0 3.3k Re 4 0 150 C1 11 1 10u C3 2 12 10u C2 4 0 100u * A load resistor added to get rid of "floating node" message RL 12 0 100Meg .model 2N3904 NPN (IS=1E-14 VAF=100 + Bf=300 IKF=0.4 XTB=1.5 BR=4 + CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 + TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40 Icrating=200m mfg=Philips) * Select nodes to measure voltages (transistor terminals, and power supply) .PRINT DC V(1) V(2) V(3) V(4) .ENDThe temperature was changed for each simulation run, and the SPICE BJT parameter bf "Ideal forward beta" was set to the rated minimum and maximum to get the following result:
These results for Vc show that a collector bias point is obtained that is well controlled over the full range of -40C to +125C temperature extremes, varying by about +/- 8% at a beta of 300, and +/- 9% at a minimum rated beta of 100.
Note that this bias circuit is also applicable to common-base and common-collector amplification stages. In the case of the common-collector amplifier, the collector resistor is usually not necessary, and as the output is taken from the emitter, the emitter voltage is raised to about half Vcc.
The above bias example applied to an NPN bipolar transistor. In the case of a PNP transistor, all the voltages and currents are reversed, for example, there would be a -12V power supply (Vee), or the emitter circuit could go to a +12V supply, but it would have to be well decoupled to ground at AC because noise signals on the supply could enter the emitter circuit and be amplified in common-base mode. In such cases the emitter decoupling capacitor is normally connected to ground, not the power supply.
Collector-Base current feedback BJT biasingIf we place the nominal collector voltage at Vcc/2=6V (ignoring the Vce(sat) minimum excursion at the collector, because this is typically less than 1V) then the voltage across the bias resistor is Vdd/2-Vbe, and the current (using the nominal beta) is Ic/200. Noting that Vbe is also a small voltage compared with 12V, and the voltage drop across both resistors is now approximately the same, then the bias resistor value is simply beta times the collector resistor = 510 * 200 = 100k ohms to the nearest preferred value.
Carrying out a SPICE simulation of this circuit gives the following result:
These results for Vc show that a collector bias point is obtained that varies by about +/- 20% at nominal beta over the full range of -40C to +125C temperature extremes.
The temperature stability is not as good as the emitter feedback circuit, which leads designers to avoid it for extended temperature ranges or for transistors with a wide range of beta, but is practical for many purposes, and the single stage gives a voltage gain of about 47dB, saving 2 resistors and an emitter decoupling capacitor. These are strong incentives for making it a popular circuit for discrete designs.
Introduction to FET Transistor BiasingFor the purpose of biasing discussions, the principal difference between BJT and FET devices is that they are voltage-controlled devices. Therefore, the operating point for the output (drain current and voltage) is set by ensuring that the voltage on the gate (or gates, in the case of dual-gate devices) is the correct voltage. This is complicated by the variety of different types of FET which have differing relationships between the gate voltage and the drain current.
In a FET circuit, by analogy to a bipolar common-emitter amplifier, the FET gate is analogous to the BJT base, the FET source is analogous to the BJT emitter, and the FET drain is analogous to the BJT collector. In fact, a better analogy would be to the valve, which is also a voltage-controlled device, in which case we have the gate analogous to the grid, the source analogous to the cathode, and the drain analogous to the anode (plate).
The FET operates by the effect of the electric field generated by the gate voltage on the flow of electrons through a single type of semiconductor (P or N type), known as the channel, between the source and drain electrodes. In an N-channel FET, the drain is positive with respect to the source, usually connected through a load circuit to a positive power supply. In a P-channel FET, the drain is negative with respect to the source, usually connected through a load circuit to a negative power supply.
Over a range of a few volts, the gate-source voltage of a FET causes the drain current to increase from zero (the "pinch-off" condition, where the gate field has reduced the conducting region of the source-drain path to virtually nothing) to a maximum or saturation current. The range of drain currents available may vary from a few mA for a small-signal FET to many amps for a power FET.
Because the gate-source voltage of a FET is not such a good approximation to a constant value as a bipolar transistor's Vbe voltage, the classic emitter-feedback bias circuit does not work as well for FETs, although it can still be useful as the transfer characteristics of FETs do not tend to vary as wildly as the current gain of a BJT with temperature. In some types of N-channel FET, the gate-source voltage may have to be negative with respect to the source, which implies a negative power supply for the gate bias network, although if there is a resistor in the source circuit then a negative voltage range equivalent to the voltage drop across the source resistor is available via the connection of the gate resistor network to the ground.
Junction FET (JFET)In a Junction FET, the gate is a semiconductor junction formed on the source-drain channel (so it would be P-type for an N-channel FET, and N-type for a P-channel FET). If the gate-source voltage is forward biased (Vgs>0V for N-channel, or Vgs<0 for P-channel) the gate begins conducting, which is usually undesirable as at this point strong signal distortion occurs or if the gate is connected to a low-impedance source, a damaging level of current could flow. Junction fets are normally operated with the gate-source junction reverse biased, and are designed for the gate-source operating voltage to be negative for N-channel, or positive for P-channel.
In an insulated-gate FET (IGFET), or metal-oxide-semiconductor FET (MOSFET), the gate is an electrode or semiconductor layer separated from the source-drain channel by an insulating layer. This allows the FET to be designed to operate over a range of voltages that overcome the forward-bias junction limitation of the Junction FET, as well as considerably reducing gate leakage current.
Given the possibility of positive gate voltages, the N-MOSFET source-drain conduction channel can be eliminated. Instead, a P-type substrate between the N-type source and drain regions is turned into an N-type conduction channel when a positive gate voltage is applied, which attracts electrons from the source into the region next to the gate, effectively repelling the holes away from the gate. This type of MOSFET is known as an enhancement-mode device, which does not conduct if the gate is at zero volts relative to the source, but requires a positive voltage to begin conduction (As usual, reverse N and P types and voltages for the P-MOSFET description).
Because the gate-source voltage for a FET or MOSFET varies significantly from one device to another due to normal manufacturing spreads, it is more difficult to devise an acceptable bias circuit for a linear FET stage. Often a multi-stage circuit will be designed with overall negative voltage feedback to ensure that the gate bias conditions for each FET are obtained for a desired output.
Substrate BiasMOSFETs often have an extra terminal connected to the device substrate (or body). The main MOSFET structure is built on top of this substrate, which is in contact with the channel structures. This terminal is sometimes accessible in discrete devices, or may be internally connected to the source. In integrated circuits, the substrate is common to a number of devices.
It is necessary to ensure that the substrate is always reverse biased with respect to any potential junctions formed between it and the channel, so normally the substrate is connected either to the source terminal (zero bias), which may be done internally so that the device doesn't have an external pin for the substrate, or a pin may be provided to connect the substrate to a voltage more negative than the source (or more positive for P-channel). The substrate must always be biased to the largest potential reverse bias in the circuit that could appear on any of the other terminals. For example, the most negative power suppy rail for N-MOSFETs and the most positive power supply rail for P-MOSFETs. The substrate should also be well decoupled for AC signals to be effectively at signal ground. If a substrate pin is provided, it is essential that the breakdown voltage between drain and substrate is not exceeded. Also, changing the substrate bias may have an effect on the device capacitances. It is therefore usually a good idea to consult the manufacturer's data sheet carefully if there is an external substrate connection on a MOSFET.
FET Self-biasThe self-bias method works in much the same way as the self-bias method used for valve stages. It can be used for JFETs and depletion-mode MOSFETs.
An example of an N-channel JFET is the 2N5484 (equivalent to 2SK104 and ECG312). It can be used for high frequency amplification up to 400 MHz. According to the Temic Semiconductors data sheet for the 2N/SST5484 Series, Vgs(off) is -0.3 to -3 V, IDSS Min (mA) is 1mA and IDSS Max (mA) is 5mA The data sheet gives parameters for Vds=10V and 15V, so 15V seems a reasonable choice for Vdd (it must of course be less than the gate-source breakdown voltage of 25V). The Idss(min) value is the worst-case value for drain current at a gate-source bias voltage of 0. If we designed for a higher Id, the gate bias could exceed 0V which is not allowed for JFETs. We should also keep the gate bias well below 0V, because the AC input to the JFET will take the peak gate voltage above the DC bias level. The Circuit Voltage Gain vs. Drain Current graph shows that voltage gain increases at lower drain current (this may not be the case at high frequency though) and states assumptions of Vdd=15V, Vds=5V, and Rl(Rd) = 10V/Id. Therefore, if we choose Id=0.5mA, Rd=20k. Looking at the Transfer Characteristics for Vgs(off)=-2V, the Vgs value for an Id of 0.5mA is approximately -1.5V. This suggests a source resistor of 1.5/0.5 = 3k, changed to 3.3k which is a more common preferred value. The resulting bias circuit is shown below.
The main source of doubts about JFET self-biasing are the wide range of Vgs(off) values that manufacturers often quote. Typical transfer characteristics are given only for Vgs(off)=-2V and Vgs(off)=-3V, but the minimum was -0.3V. Fortunately, the self-bias method does provide negative feedback which tends to compensate.
Immediately at turn on, the gate and source are both at zero volts, allowing the full Idss current to flow. This current charges up the source bypass capacitor and eventually the current must stabilise with a DC flow through the source resistor that pulls the source voltage above reference ground, causing an equivalent reverse bias voltage to appear between the gate and source, since the gate is connected to ground via a high-valued resistor. But as the self-bias voltage increases, this reduces the drain-source current until an equilibrium value is reached. Any change in Id caused by temperature effects or changes in Vdd will cause a change in the self-bias voltage across Rs that will tend to cancel the change in Id.
Exporting the SPICE netlist using the illustrated circuit file JFETBias.CCT with Circuit Scribe, and adding necessary lines for LTC SwitcherCAD to do a DC operating point analysis, we get the following SPICE input file:
* Model for LTC SwitcherCAD to check DC bias voltages * Sets the temperature *.TEMP -40 .TEMP 25 *.TEMP 125 * The power supply V1 3 0 DC 15 * This does an AC analysis. * .AC DEC 10 100HZ 10MegHZ * This does a DC operating point analysis. .OP * VIN is the input for this circuit. VIN 5 0 AC 1. * The netlist exported from Circuit Scribe: *SPICE JFET Biasing Rd 3 2 20k Rg 1 0 1Meg Rs 4 0 3.3k C1 5 1 0.1u C3 2 6 10u C2 4 0 100u * NB ensure node order is drain, gate, source J1 2 1 4 2N5484 * A load resistor added to get rid of "floating node" message RL 6 0 100Meg .model 2N5484 NJF(Is=.25p Alpha=1e-4 Vk= 80 Vto=-1.5 + Vtotc=-3m Beta=3.0m Lambda=10m Betatce=-.5 + Rd=10 Rs=10 + Cgs=4p Cgd=4p Kf=3e-17 mfg=Siliconix) * Select nodes to measure voltages (transistor terminals, and power supply) .PRINT DC V(1) V(2) V(3) V(4) .ENDThe temperature was changed for each simulation run to get the following result:
The DC level at the drain isn't critical for the typical application of this kind of JFET circuit, which is in small-signal amplification, and the self-bias circuit works sufficiently well in most cases. In an RF circuit, an inductive load is likely to be used rather than a resistor, which puts the full Vdd level on the drain, making variations in drain current less important and potentially allowing a lower Vdd to be used.
Exactly the same self-bias principle can be used for biasing depletion-mode MOSFETs, although their most common application is as power devices used as switches, where the gate bias level will be switched between voltages guaranteeing fully-on and fully-off channel conduction.
This technique can also be used for enhancement-mode devices, provided that the source resistor is returned to a suitable negative voltage (or positive for P-channel FETs).
FET Drain-gate feedback biasEnhancement-mode MOSFETs may be biased using a resistor network between drain and gate, since the drain voltage decreases with increasing drain current and hence increasing gate voltage. This provides negative DC feedback. To set the drain and gate voltage, a potential divider must be used to derive a gate voltage from the drain voltage.
In the above circuit, an enhancement mode FET is biased such that the quiescent Vd=4.3 V at 25C, with Vg=2.15 V. The potential divider divides the drain voltage Vd by 2, since the gate has very low leakage current. The MOSFET stabilises at the operating point at which the gate voltage causes sufficient drain current to flow to satisfy the potential divider ratio. The MOSFET drain current is 0.51 Amps which causes a power dissipation of 2.2W in the MOSFET, and 7.7W in the drain resistor. This circuit provides 30dB of voltage gain with a bandwidth exceeding 10Hz to 1MHz, and for a sine input of 0.05V peak, produces 1.75V peak into an 8 ohm load (0.2 W) with a THD of 7.6%.
This isn't a particularly good circuit for a power amplifier, as it is very inefficient, but serves to illustrate the principle of using voltage feedback bias.
This bias arrangement can be used for microwave enhancement mode FETs, for example the Agilent ATF-55143 PHEMT, which requires a gate-source potential of about 0.47V for a nominal drain current of 10mA and Vds of 2.7V.
This technique can also be used for depletion-mode devices, provided that the resistor Rg1 is returned to a suitable negative voltage (or positive for P-channel FETs).
As MOSFETs used for small-signal linear amplifiers tend to be depletion mode, where source-resistor self-bias can be used without the need for a negative supply, this type of biasing has not been used very often; enhancement-mode MOSFETS are usually used as switches, where the ideal characteristic is the switching on and off of an output using an input logic level of the same polarity. However, by applying the general principles shown above, the use of such devices could be extended to many other applications, which is useful as they are common low-cost devices.
In DC coupled circuits (for example, an audio amplifier), where there is an overall feedback loop, an enhancement mode FET can conveniently take the place of a BJT stage, without much alteration, as the FET's gate-source bias offset and the BJT Vbe voltage drop are of the same polarity; usually the DC operating point of the driving stage can be permitted to shift to allow for the difference in voltage magnitude.
MESFETsA MESFET (MEtal Semiconductor FET) is similar to a JFET, except that the PN junction at the gate is replaced with a metal-semiconductor Schottky barrier contact. A MESFET is normally a depletion mode device but enhancement types can be designed (by using thin channels with low doping). The Schottky junction is particularly convenient for compound materials such as Gallium Arsenide, and MESFETs are used for high frequency and high power RF devices. When the devices are made from Gallium Arsenide, they are also referred to as GaAsFETs, or GaAs MESFETS.
At frequencies used by microwave MESFETs, decoupling a source resistor to ground without introducing significant impedance (that may reduce gain or cause RF instability) is difficult. Also, some devices may rely on heat dissipation through the source terminals to ground which precludes inserting other components in series. The MESFET gate and drain terminals are typically connected to their DC bias levels through an inductive or transmission-line network that passes DC but blocks the signal frequency.
To stabilise a MESFET's DC operating point, therefore, a feedback arrangement may be used which attempts to measure the drain current and control the gate voltage in a feedback control loop, including active devices ancillary to the MESFET itself. This can be justified for expensive RF MESFETs because precise control of their operating point is essential for keeping them within safe operating limits, and obtaining optimum performance. The feedback can be implemented using a purpose-built IC, such as the fixed bias generators made by Zetex Semiconductors for GaAsFET Low Noise Amplifier and active mixer applications, which integrate op-amp based circuits with settings for drain voltage and current together with a negative bias supply generator, or with a simple transistor circuit in conjunction with a negative bias supply as is shown below.
This example illustrates a bias circuit for a FET made by Agilent, which is a a low noise, high dynamic range PHEMT (Pseudomorphic High Electron Mobility Transistor) in a surface mount SOT-343 surface mount package suitable for low noise amplifiers (LNA) in base stations and wireless LANs in the 450 MHz to 10 GHz frequency range. A PHEMT device uses a compound semiconductor made up of indium, gallium and arsenic atoms in a very thin layer on a GaAs substrate. However, as far as the FET technology is concerned, for the purpose of DC biasing all we need to know is that the device has the typical characteristics of a depletion mode FET, where for an N-channel device the drain channel begins to conduct when the gate-source voltage exceeds a certain negative voltage.
This active bias circuit sets the operating drain current and voltage of the microwave MESFET by sampling the drain current of Q3 using a resistor Rd in series with the drain supply. The RF circuit elements around Q3 are not shown, but they have no significance at DC for biasing considerations (although sometimes modifications may be needed to maintain stability of the feedback circuit, depending on what capacitance and inductance values are present in the RF circuit). The BJT transistor Q2 has its base potential fixed by the potential divider across the 5V supply (which is assumed to be regulated). If we assume that the drain current of Q3 is initially zero, and the magnitude of the voltage at Q2 base exceeds Vbe (relative to the Vdd supply rail), then Q2 must be fully turned on, since several mA of base current must flow through Rb2. This pulls the gate voltage of Q3 up towards Vdd. Rc1 limits the maximum gate voltage, which for microwave GaAs FETs may have a maximum rating of only a few volts. With increased gate voltage, Q3 therefore reaches turn-on gate bias, allowing drain current to flow, until sufficient voltage is dropped across Rd to reduce the voltage across Q2 base-emitter to a normal bias level. There is overall negative feedback around this loop, so that the drain current of Q3 is stabilised. If the drain current increases, this reduces the Vbe bias across Q2, reducing its collector current, which allows the gate voltage of Q3 to drop, which reduces the drain current of Q3.
The bias design procedure assumes that a steady state DC operating point has been reached in the feedback loop:
The value of Rd is chosen so that Vd is close enough to the nominal Vds (4V) of Q3 when the nominal drain current (60mA) is flowing, which with a 15 ohm resistance produces a voltage drop of nearly 1V across Rd. Since Q2 Vbe is approximately 0.7V, Vb must be 1.7V below Vdd, i.e. 3.3 V.
A SPICE model of this bias circuit gives the following operating point values:
To generate the supply voltages required for this bias circuit requires a couple of standard voltage regulator ICs, as shown below:
This circuit provides regulation and noise suppression for the Vdd supply from a 12V input via IC1, which could be adjusted for different Vdd voltages using R1/R2. The negative supply, which does not need to supply much current, is derived from the 5V supply using voltage inverter IC2 (which provides an additional layer of noise suppresion from the main voltage input).
Note that if the negative voltage supply should fail, it is possible for the depletion mode FET to conduct fully, and (especially with higher power devices) exceed drain current or power dissipation limits. A power supply switching enhancement-mode MOSFET (Q1) is provided which only turns on when the negative voltage supply is present. Due to its low on resistance, only a few mV are lost in this transistor.
Characteristic Curves and Load LinesThis method of analysis is somewhat more elaborate than the simple and practical approach of picking a DC bias point for a device's output half way between the minimum and maximum voltage swings (e.g. Ve + Vce(sat) for bipolars, to Vcc), and working through all the current bias and resistor values. For many applications, where a device is used well within its maximum current, voltage and power limits, it isn't needed. It is helpful to understand the dynamics of device output, and essential when designing a circuit to make the most of a device's power capability.
One way of looking at the biasing active devices is to consider it as the selection of the device's operating point on its Characteristic Curves.
These show how the output current and voltage of an active device are related to the input voltage or current (and also how the output current and voltage are related).
As an introductory example, consider a PN junction diode connected in forward bias to a power supply, say Vcc=5V, through a load resistor Rl=2.2k (This simplifies the analysis a bit, as there is no control input). You can obtain diode current-voltage characteristics from a data sheet, if the manufacturer is informative enough to provide it.
This simple arrangement allows us to check the analysis against a simple calculation that assumes a 0.7V junction drop, so that the current (i) is (12-0.7)/2.2 = 5.14 mA.
The current "i" in a PN junction diode with a voltage "v" across it can be described mathematically by Shockley's ideal diode characteristic equation:
i = Is * (exp(qv/nkT) - 1)
= Is * (exp(v/0.0258n) - 1)
where Is is the reverse-bias saturation current (typically 2.52 nA for a silicon 1N4148,
and around 1 uA for germanium signal diodes),
k is Boltzmann's constant (1.38054E-23 J/K),
T is temperature in degrees Kelvin
q is the charge on an electron (1.602189E-19 C)
n is the "emission coefficient", "Ideality Coefficient" or "ideality factor", typically between 1 and 2.
Note that you can replace the factor kT/q with the voltage
25.8 mV, which is equivalent at a fixed T of 300 degrees Kelvin, i.e. 27 degrees Celsius).
(This equation is inaccurate for higher currents as it does not take into account additional ohmic resistance in the diode)
As regards the resistor load, the current characteristic we are interested in is not current versus voltage across the resistor (which would be a straight line through the origin (0,0) with a slope of Vr/R), but instead, we want to know the resistor current according to the voltage on the diode, when the other end of the resistor is connected to the power supply voltage.
The voltage drop across the load resistor is (Vcc - v), therefore Ohm's law says the current i in the resistor must also be given by:
i = (Vcc-v)/Rl.
The difficulty with most active devices is that their characteristics are non-linear, and the operating points are not easily calculated mathematically from first principles (although in the case of the PN junction diode, often it is an appropriate engineering assumption that the diode drop is 0.7V in practical design).
Before PCs and SPICE, it used to be easiest to solve this graphically, as follows.
On this chart we have a curve of the diode current versus voltage according to the above formula. Because of its exponential character, its current appears to increase very rapidly above a voltage of about 0.5 V, where the formula predicts 58 uA, and the voltage across the diode is 0.7V for a current of about 5 mA (The data sheet for a Philips 1N4148 specifies forward voltage 0.62 V (min) to 0.72 V (max) for an IF = 5 mA)
The straight line on the chart is drawn between a current of 50mA on the current axis (where voltage is zero), and a voltage of 5V on the voltage axis (where current is zero). This corresponds to the current/voltage relationship for a resistor of value 100 ohms, connected in such a way that when the voltage plotted on the chart is zero, the current is 50mA, and when the voltage is 5V, the current is zero. This is what you might expect if a variable voltage (e.g. the voltage across the active device) is connected in series with the resistor and a 5V power supply; and it is called a load line. It shows what the load current would be for any given load voltage in series with the supply voltage. On the other hand, the active device curve shows what the device current would be corresponding to the device voltage at any point along the curve.
If the device and the load are connected in series, both of the curves must apply simultaneously, and the only way this can happen is where they intersect (circled in red). In this case, by reading the graph coordinates for this point, it tells us that the diode will develop a voltage across it of about 0.8V, and the current will be just above 40 mA (which we can also calculate as (5-0.8)/100 = 42 mA).
What if there is another variable factor involved, such as temperature? This would shift the diode curve mostly left or right, while the resistor load line does not change, and the intersection of the two points would follow the diode characteristic. We will use a similar concept to account for active devices which have a signal-derived input.
I have selected the IRF520 MOSFET (a 9.2A, 100V N-channel MOSFET) for a practical illustration of the characteristic curve. The following diagram shows the concept behind the MOSFET characteristic curves (although in practice, a pulsed test system is likely to be used to avoid burning out the device at high drain voltage and current).
The MOSFET characteristic curves are a family of curves, each of which is a plot of drain current versus drain voltage for a particular gate voltage.
The output operating point is the intersection of the load line and the curve of drain current versus drain voltage (for a particular input gate voltage). If you change the gate voltage, the Id/Vd curve changes, and hence the operating point changes. So, for a gate voltage of 4V there is an intersection near 25V and 0A. When the gate voltage increases to 4.5V, the intersection moves along to near 22V and 1A. This continues similarly to a gate voltage of 7.5V or more, at which point the MOSFET drain voltage reaches a limiting saturation level of about 2V at 8A and the MOSFET is behaving like a resistance, Rds(on), of about 0.25 ohms.
The drain current characteristic curves on this plot (in blue) are a family of similar curves which start at zero drain voltage and current, increase in current rapidly up to a "knee" or "corner" and then level off with the drain current not increasing much as the drain voltage increases further.
Overlaid on the chart are limiting curves for power dissipation and drain current (assuming continuous operating conditions, which should normally be assumed for anything other than pulsed conditions described in the device data) Since the maximum device dissipation is 60 Watts, the product of drain current and drain voltage must be less than 60, which results in the curved red line. To avoid overheating the MOSFET, operating points must lie to the lower left of this line. The maximum continuous drain current is 9.2 A, so the operating point must also lie below the green line. So, to get maximum safe power out of this MOSFET, the black load line is positioned as shown, just inside the drain current and power dissipation limits. In a similar manner to the load line described for the diode, this load line describes an active device controlling a load that draws 9A when the active device is fully on (assuming an ideal voltage drop of 0 V), and is connected to a 25V power supply. Therefore, the load resistance is 25/9 = 2.8 ohms. A larger resistance could be used of course, resulting in lower drain currents. Let's assume a 2.8 ohm load anyway. If our circuit generates an ideal sine wave across the load over the whole voltage range, we would have a range of +/- 12.5 V peak, and +/- 4.5 A peak relative to the average. The AC RMS power developed in the load is then 0.25*12.5*4.5 = 14 W. Of course, to obtain this power usefully in a loudspeaker would require a transformer so that the loudspeaker is DC isolated, as loudspeakers can not tolerate a standing DC bias.
Selecting the quiescent operating point is a matter of checking the extent of the possible output signal excursion and finding the mid-way point.
When the MOSFET is fully turned on, the on resistance limits the minimum drain voltage corresponding to point A. When the MOSFET is virtually turned off, the drain voltage approaches the power supply voltage as shown at point B. The optimum operating point (assuming a Class A amplifier) is therefore centred between these two points, at point M. Note how point A is near a "knee" in the characteristic curve. This is almost inevitable for any device that has this type of curve, as point "A" is near the asymptotic line that defines the resistive channel operating region, and there will always be some value of gate voltage that causes the curve to break away to the right into the current-limiting region.
Point M shows that the gate bias will need to be around 5.75V, and a bias feedback circuit would need to be designed to stabilise the drain voltage at around 13V.
Note that as the gate voltage varies, the spacing between characteristic curves and hence the drain voltage or current is similar for equal steps around the bias point M. However, near point A or B, the curves get closer together, resulting in the peaks of any sine wave driving to those points becoming squashed or clipped, and producing distortion in the output signal. To avoid distortion, it is obviously better to avoid driving the output as far as points A and B and keep well within the range. Of course, this means you have to accept less output power than the maximum available (unless you take some other means to reduce distortion, such as negative feedback).
It is no coincidence that the optimum bias point "M" is also closest to the maximum power curve. This is typical of a Class A amplifier stage, that its bias point tends to cause it to dissipate maximum power with zero signal and makes it the most inefficient class of amplifier. The power dissipation at point "M" is 12.5*4.5=56.25 W in the MOSFET, and the same in the load resistor, making a total power dissipation of 112.5 W, and a maximum efficiency of 14/113 = 12%. With the power level backed off to avoid distortion, the efficiency is likely to be no more than about 10%, which is typical for a class A amplifier.
This biasing demonstration was simulated using the LTC SwitcherCad program, with the following circuit:
The simulation applies a sine wave input to the FET that is stepped from 0.5 to 2.0 V peak in steps of 0.5V. The gate bias is set to 5.75 V, as mentioned above, supplied through a resistor to isolate the AC signal from the low impedance of the DC bias source. Instead of a resistor connected to 25V, the output is via a transformer to the same load resistance (this is how you would ensure maximum power is supplied to the load without subjecting it to a constant DC bias). Because there is now no DC resistance present between the drain and the power supply, the power supply voltage is set to 12.5V to match the bias point M. The transformer action, creating an impedance to the AC signal of 2.8 ohms in the drain circuit, causes the drain voltage to swing either side of this bias voltage, giving the equivalent voltages and currents at the drain as if the load resistor had been connected directly to a 25V power supply.
The resulting plot shows how the sine wave output becomes obviously distorted as the voltage is increased, and the non-linearities near operating points A and B are approached:
Load-line analysis proceduresFollowing through the load-line graphical method, you can see that biasing an active device for maximum output power requires several constraints to be satisfied:
- Keep within Maximum device current
- Keep within Maximum device voltage
- Keep within Maximum device power
- Keep within any other device limitations (i.e. you should study the manufacturer's data sheet)
Consider the following two different starting points:
A: Select a device output bias (quiescent) current (Ioq)
less than 1/2 of the device limit, e.g. Id(max).
The bias voltage (Voq) is the maximum power Pd / Ioq.
Is Voq*2 greater than the maximum device voltage (e.g. BVdss)?
If so, reduce Ioq by multiplying by a factor BVdss/(Voq*2), or try "B" instead.
For the IRF520, we get Ioq=4.6 A, and Voq=13V; checking, Voq*2 is less than BVdss (100V).
B: Select a device output bias voltage (quiescent) voltage (Voq)
less than 1/2 of the device limit, e.g. BVdss.
The bias current (Ioq) is the maximum power Pd / Voq.
Is Ioq*2 greater than the maximum device current (e.g. Id(max))?
If so, reduce Voq by multiplying by a factor Id(max)/(Ioq*2), or try "A" instead.
For the IRF520, we get Voq=50V, and Ioq=1.2A; checking, Ioq*2 is less than Id(max) (9.2A).
For the IRF520, both starting points work. The difference is that "A" results in a load impedance of 26/9.2 = 2.8 ohms, indicating the minimum load impedance that the device can drive at full power, and "B" results in a load impedance of 41.7 ohms, indicating the maximum impedance that the device can drive at full power.
It is clearly going to be useful to design the circuit to drive a particular load impedance, which must be takein into account as part of your starting point (it corresponds to the negative slope of the load line). Graphically, you would find the slope of line corresponding to the impedance, and keeping the slope constant, move it towards the maximum power, current and voltage constraints until you reach one of them.
However, it is not difficult to use a formula-based analysis to achieve a similar result.
For example: Let the quiescent voltage and current at point
"M" be called Voq and Ioq respectively,
RL is the load resistance,
Pmax is the maximum allowed device power dissipation
Pdc is the actual device power dissipation
Then the ratio Voq/Ioq will be RL, and the product Voq*Ioq must be no more than Pmax (select a value Pdc). This can be solved as a pair of simultaneous equations (ignoring the effect of the knee voltage for the time being):
Voq/Ioq = RL
Voq*Ioq = Pdc
Voq2/RL = Pdc
Voq = sqrt(Pdc*RL)
Ioq = Voq/RL
For the IRF520, using Pdc=Pmax=60, picking an RL between the limits previously
calculated (2.8 to 41.7 ohms) at 20 ohms,
Voq = sqrt(Pdc*RL) = 34.6V.
Ioq = Voq/RL = 1.73A.
We should also check the maximum current and voltage, but since we have already chosen RL to be between the minimum and maximum drivable load resistance, this has been taken care of.
When designing a power output stage to make the most of a device's limits, it is important to consider whether you want to use the device at its limits, or back off from those limits, or perhaps select a more powerful device for the same operating point, the principal reasons being:
- Tolerance and drift: If the operating point changes due to ageing, temperature, or varies according to tolerance variations in bias components, it is less likely to take the device over its safe limits.
- If operating the device at an elevated ambient temperature, a derating factor must be applied compared with the device limits at nominal ambient.
- The reliability of devices decreases exponentially with increase in steady state temperature. As a general rule of thumb, the failure rate doubles for every 10 degrees C rise in temperature.
Accounting for saturation voltageThe device saturation voltage (the voltage remaining across it when it is turned on to maximum current flow) subtracts from the voltage swing available from an output stage. In the preceding sections on load line analysis, I have somewhat glossed over the effect of this, but let's now take another look at the chart with the minimum voltage explicitly labelled as Vmin:
Placing Voq at the mid-point between Vmin and Vmax makes:
Voq = (Vmax-Vmin)/2
Vmax = 2*Voq-Vmin
Placing Ioq at the mid-point between Imin (which is zero) and Imax makes:
Ioq = Imax/2
Imax = 2*Ioq
The total load resistance is the slope of the load line (times -1), which is
RL = (Voq-Vmin)/(Ioq)
RL = 2*(Voq-Vmin)/Imax
The device quiescent DC power dissipation is Voq*Ioq:
Pdc = Voq*Ioq [<= Pmax for the device]
Pdc = Voq * Imax/2
The total output power to RL is the product of the RMS current and voltage,
i.e. 1/2 the product of the peak current and voltage:
Pout = (1/2) * (Ioq-Imin) * (Voq-Vmin)
Pout = (1/2) * (Imax/2) * (Voq-Vmin)
Pout = Imax(Voq-Vmin)/4
The efficiency is the ratio of output power to DC power, which is:
Eff = (Imax(Voq-Vmin)/4) / (Vmax * Imax/2)
Imax cancels completely, leaving:
Eff = (Voq-Vmin)/2*Vmax
(Note that Eff would be doubled if the stage is choke or transformer coupled, because the DC supply would then just be Voq instead of 2*Voq-Vmin)
RL in terms of Pout:
Pout = Imax(Voq-Vmin)/4
Pout = (2*(Voq-Vmin)/RL)(Voq-Vmin)/4
Pout = ((Voq-Vmin)2)/(2*RL)
RL = ((Voq-Vmin)2)/(2*Pout)
Pout = RL*(Ioq2)/2
RL = 2*Pout/((Ioq2))
Operating point as a function of output power and load resistance:
To solve this, it is a useful guide to start by comparing the situation with the simplified version where Vmin was zero, and looking at how those equations are now modified when Vmin is not zero:
Voq/Ioq = RL becomes (Voq-Vmin)/(Ioq) = RL
Ioq = Voq/RL becomes Ioq = (Voq-Vmin) / RL
Voq*Ioq = Pdc remains unchanged
(Voq*(Voq-Vmin) / RL )= Pdc
Voq*(Voq-Vmin) = Pdc * RL
Voq2 - Voq*Vmin - Pdc*RL = 0
To solve this, we have to use the Quadratic Formula to get a solution, which is now ambiguous because there are two solutions (according to the sign taken by the "+/-":
Voq = (Vmin +/- sqrt(Vmin2 + 4*Pdc*RL))/2
For this to have a practical solution, the sqrt() must have a positive value, and Voq can't be less than Vmin, so the only solution of interest must therefore be:
Voq = Vmin + sqrt(Vmin2 + 4*Pdc*RL))/2
and Ioq can then be calculated from:
Ioq = Pdc / Voq
Let's put in some practical values again using the IRF520 as an example again.
Starting with a 20 ohm load resistance, Vmin of 2V, and Pdc of 60W:
Voq = (2 + sqrt(4 + 4*60*20))/2
= (2 + sqrt(4804))/2
= (2 + 69.31)/2
Ioq = 60/35.655 = 1.68A
Then, using the above formulae:
Vmax = 69.31 V
Imax = 3.36 A
Pdc = 59.9 W
Power in RL = (Vmax-Voq)*Ioq = 56.5 W
Pout = 28.3
Eff = 0.24
The results are not very different from an analysis that ignores the knee voltage, as long as the power supply voltage is large enough to swamp its effect.
InfoZip file containing Circuit Scribe project files and LTC SwitcherCad files:
2n3904curve.asc - Plots characteristic curves for 2N3904 BJT transistor
bjtbias.CCT - Circuit Scribe circuit for C-B current feedback bias
BJTBias.cir - Calculates operating point for BJT with emitter feedback
bjtcbias.CCT - Circuit Scribe circuit for C-B current feedback
BJTCBias.cir - Calculates operating point for C-B current feedback
diodeloadline.CCT - Circuit Scribe circuit for diode load line
gaasfetbias.asc - SwCAD circuit for GaAsFET active bias circuit
GaAsFETBias.CCT - Circuit Scribe circuit for GaAsFET active bias circuit
irf520.spi - Model of IRF520 MOSFET
irf520ClassA.asc - IRF520 Class A amplifier with stepped AC sine wave excitation
irf520curves.asc - Plots characteristic curves for IRF520 MOSFET
jfetbias.CCT - Circuit Scribe circuit for JFET bias
JFETBias.cir - Calculates operating point for JFET Biasing
MOSDBias.cir - Calculates operating point for Enhancement mode MOSFET with drain feedback
MOSDBias.cct - Circuit Scribe circuit for Enhancement mode MOSFET with drain feedback
For Circuit Scribe software, see: Software
Linear Technology Corporation's LTSpice (formerly SwitcherCAD 3) software:
Linear Technology - Home Page
SPICE model for 2N3904 (Philips)
.model 2N3904 NPN (IS=1E-14 VAF=100 + Bf=300 IKF=0.4 XTB=1.5 BR=4 + CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 + TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40 Icrating=200m mfg=Philips)SPICE model for 2N3904 (Fairchild)
.model 2N3904 NPN (Is=6.734f Vaf=74.03 + Bf=416.4 Ikf=66.78m Xtb=1.5 Br=.7371 + Cjc=3.638p Cje=4.493p Rb=10 Rc=1 + Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 + Xti=3 Eg=1.11 Ne=1.259 Ise=6.734 Nc=2 + Isc=0 Ikr=0 Mjc=.3085 Vjc=.75 Fc=.5 Mje=.2593 Vje=.75)