When you invoke the netlist dialog, the program determines connectivity for all the nets in the drawing (consisting of interconnected tracks, pins, and buses), checks for layout errors, shows the results in the dialog, and highlights objects on the main display that have check violations. The netlist is calculated including all pages in the layout.
The netlist dialog contains three lists. The first lists all the nets in the layout. Net number 0 is always present; this is the reference ground. Any tracks that are connected to an object with the "Force net to ground" property will be assigned to the ground net. Otherwise, the tracks will be assigned net numbers from 1 and above. The net name is taken from the label field assigned to at least one of the connected tracks. The net value is taken similarly from the value field. The "Connected" column shows how many object pins are connected to the net. The second list does the same as the first, but for buses. Since buses should not be directly connected to any pins, the "Connected" column should always contain zeroes. The list shows the bus number starting at 0, the bus name, e.g. "b[0..15]", and the bus value should you choose to use it for some reason. Buses are only used to diagrammatically indicate connections between groups of tracks, and therefore do not appear in any SPICE netlist. The net numbers are used to generate the node numbers for the SPICE netlist.
The third list gives the result of all layout checks. If all checks pass, a green tick is shown below the list with the text "No check failures detected". The checks made are as follows:
If there are check failures, you can still save a netlist file, but where there is missing data, "?" marks will be shown instead, and there may be errors in the netlist.
Objects that are not relevant to a simulation should be excluded, by right-clicking on the object, selecting "Edit object's settings and properties", and under the "Object settings" tab checking the "Exclude from Spice output" checkbox. This excludes the object from listing in a Spice output file, for example a terminal pin or ground symbol that plays no part in circuit simulation. It is usually more convenient to have the "Exclude from Spice output" property set up in a library part.
If an object has a model (e.g. transistors) the data should be entered by right-clicking on the object, selecting "Edit object's settings and properties", and under the "Parameters" tab entering the Model (e.g. ZTX109) and/or Params (e.g. 1.0) fields as required. Other fields, used for the Bill of Materials, are not necessary for SPICE simulation.
For the whole circuit, the models to be used should be entered by selecting the main menu Setup/General Properties command, and under the dialog box Models tab, enter the text for the SPICE models to be used.
If you wish, you can add your models and parameters to the SPICE netlist after generation without entering them in the Circuit Scribe project file, although it is usually more convenient to record them with the Circuit Scribe project.
You would usually be adding SPICE commands and modifying the SPICE netlist that you generate, so to avoid losing that data, take care to keep the final SPICE simulation file separate (or renamed) from the SPICE netlist that you generate from Circuit Scribe.
PSPICE version 4.03, which fits in a 1.13Mb zip file, was used for this first demonstration (if the netlist is compatible with something this old, it should be compatible with many later versions of SPICE).
This version is meant to run on OS2; fortunately (for Windows users), Windows 2000/XP/NT can support this, as provided by the system32\OS2.exe command shell and support files or Os2 subfolder in your Windows installation.
(Note: The Windows OS2 subsystem may sometimes be disabled for security reasons).
PSPICE is popular both with University faculties, where evaluation versions are often used for student assignments, and with professional engineers. The original MicroSim PSPICE is now part of Orcad's design suite. There are several versions of the free evaluation PSPICE around, for example, do a web search for "ps5_3.zip", "62awine.exe", "62plsyne.exe", "63wine.exe", "ps8_0.zip", "80dlabe.exe", "ps9_1.zip", or "91pspstu.exe".
PSPICE versions 5.3, 8.0 and 9.1 may be found here:
http://www.engr.uky.edu/~cathey/pspice061301.html
PSPICE versions 5.1 and 7.1 may be found here:
http://www.cmsa.wmin.ac.uk/~alison/pepsig/SW/pspice.html
Our example will use the following SPICE model:
.MODEL ZTX109 NPN IS=1.8E-14 ISE=5.0E-14 NF=.9955 BF=400 BR=35.5 +IKF=.14 IKR=.03 ISC=1.72E-13 NC=1.27 NR=1.005 RB=.56 RE=.6 RC=.25 +VAF=80 VAR=12.5 CJE=13E-12 TF=.64E-9 CJC=4E-12 TR=50.72E-9 MJC=.33 |
The example project file "BJTAmp.cct" contains a bipolar transistor amplifier circuit containing the relevant SPICE data for export to a SPICE netlist.
The terminal pins P1 and P2 have been excluded from SPICE netlisting, and the earth symbol has been excluded from netlisting, which automatically excludes it from SPICE netlisting (these properties were defined when the pin and earth objects were placed in the library file, so they don't have to be set every time you place the component).
The resistors and capacitors are modelled using SPICE models built-in to the simulator, and do not require any model or parameter information to be entered. However, the value string is used in the SPICE netlist, and must conform to the SPICE conventions regarding element values and suffixes (e.g. the suffix Meg used for 1000000 ohms). The transistor Q1 has the model field set to ZTX109 and params field set to 1.0.
When you export the SPICE netlist, you get the following file:
*SPICE BJT Amplifier C1 5 1 1U C3 2 4 1U C2 0 6 100U Q1 2 1 6 ZTX109 1.0 R1 1 3 82k R4 2 3 4.7k R2 0 1 22k R3 0 6 1.8k C4 0 3 100u .MODEL ZTX109 NPN IS=1.8E-14 ISE=5.0E-14 NF=.9955 BF=400 BR=35.5 +IKF=.14 IKR=.03 ISC=1.72E-13 NC=1.27 NR=1.005 RB=.56 RE=.6 RC=.25 +VAF=80 VAR=12.5 CJE=13E-12 TF=.64E-9 CJC=4E-12 TR=50.72E-9 MJC=.33 .END |
Some additional information must be added to the SPICE netlist in order to generate a SPICE simulation. This may depend on the type of SPICE software that you use to do your simulation. The main object of the extra lines is to set up the simulation parameters and measurements that you want in your simulation.
We will add the following header to the netlist (you need to use a plain ASCII text
editor to do this), to simulate using the PSPICE simulator.
* This command sets options for the run. .OPT NOMOD NOPAGE RELTOL=.001 * Sets the width of the output to 80 columns. .WIDTH OUT=80 * Sets the temperature for the run to 35 degrees celsius. .TEMP 35 * This does an AC analysis. The real and imaginary response of the circuit * is calculated as the inputs are swept from 100 hertz to 10 megahertz * by decades with 10 points per decade. The only AC input this circuit has * is VIN. This is a linear analysis. .AC DEC 10 100HZ 10MegHZ * Transient analysis .TRAN 1ms 100ms 0ms .1ms * The following statements describe the circuit |
* VIN is the input for this circuit. VIN 5 0 PULSE(0 0.1 10m 1n 1n 40m 100m) AC 1m * The power supply VCC 3 0 DC 12 * Gummel-Poon bipolar transistor model: * forward beta = 80, base resistance = 100 ohms, * collector-substrate capacitance = 2 pF, * forward transit time = 0.3 ns, reverse transit time = 6 ns, * base-emitter capacitance = 3 pF, base-collector capacitance = 2 pF, * forward Early voltage = 50 V. *.MODEL QNL NPN (BF=80 RB=100 CCS=2PF TF=0.3NS TR=6NS CJE=3PF CJC=2PF *+ VA=50) *ZETEX ZTX109 Spice model Last revision 4/90 * |
* These commands provide print and plot output for selected voltages * and currents. The plots are the so-called "line printer" plots. * That is, plots made out of characters. To get real, high-resolution * plots you need to use Probe; it is invoked by the .PROBE command. .PRINT DC V(2) V(1) V(6) .PLOT AC V(2) .PLOT TRAN V(2) .PROBE |
After simulating with PSPICE, the result plotted for the output of the BJT amplifier at pin P2 (Node V(2) at C3) appears as follows:
Considering that the input was set to be a 1mV source, the peak gain of this amplifier
is 166, or 44dB.
The DC results from the SPICE simulation were given as:
| Description | Node | Voltage (V) | Current (mA) |
| Q1 Base | 1 | 2.4819 | |
| Q1 Emitter | 6 | 1.8581 | |
| Q1 Collector | 2 | 7.1636 | |
| Vcc | 3 | 12 | 1.145 |
These are consistent with the expected voltages as designed for a 1mA collector bias current.
The emitter resistor has 1.858V across it, so the current flow is expected to be 1.858/1.8 = 1.03 mA. The base bias chain has 12V across it, and should (ignoring the base load) take 12/104 = 0.12 mA. The total of these estimates is 1.15 mA, which is consistent with the SPICE simulation load current of 1.145mA at the 12V Vcc node.
The rule of thumb for the gain is 40 times the voltage drop across the collector resistor. This is equivalent to using the formula Av = (Rl * Ie) / 25, where Rl is in ohms, and Ie is in milliamps. Note that Rl*Ie (in ohms and mA) = 1000 times the voltage drop (in Volts) across the collector resistor Rl*Ic, and therefore we divide 1000 by 25 to get the factor of 40.
This gives 40*(12-7.16) = 194 or 46dB (2dB error is not too bad for a rule of thumb).
The example project file "opamp741.CCT" contains a bipolar transistor simulation of the classic 741 op-amp, using 2 types of NPN, and 2 types of PNP bipolar transistor, with the relevant SPICE data for export to a SPICE netlist.
The circuit uses the following SPICE models for the transistors:
.MODEL NPN NPN BF=160 RB=100 CJS=2P TF=0.3N TR=6N CJE=3P CJC=2P VAF=100 .MODEL NPQ NPN BF=160 RB=100 CJS=2P TF=0.3N TR=6N CJE=3P CJC=2P VAF=100 IS=2P .MODEL PNP PNP BF=20 RB=20 TF=1N TR=20N CJE=6P CJC=4P VAF=100 .MODEL PNQ PNP BF=20 RB=20 TF=1N TR=20N CJE=6P CJC=4P VAF=100 IS=2P |
The circuit was based on a model from the book "SPICE" (E. Hoefer, H. Nielinger),
which appears on a web site by Hugo Coolens:
http://users.skynet.be/hugocoolens/spice/ua741/ua741.htm
Because the model already had netlist node numbers allocated, each net in the circuit was labelled (on at least one track) with a numeric track label. This forces the netlisting to use that number for the track's net number.
The SPICE simulator used in this case was the Linear Technology Corporation's SwitcherCAD 3 software, version 2.13p.
Link:
http://www.linear.com/index.jsp
To carry out the simulation, the SPICE netlist saved from Circuit Scribe, using the same
procedure as for Example 1, is placed into a SUBCKT declaration, the subcircuit
is connected up as an op-amp non-inverting unity gain buffer, and suitable
simulation inputs and settings are added to create the following netlist file
that can be read in by SwitcherCAD:
* Sets the temperature to 35 degrees celsius.
.STEP TEMP LIST 35 35
* This command does a DC sweep.
*.DC Vin -15 15 0.05
* This command finds the DC operating point
.OP
* This command does a small-signal transfer function calculation assuming
* VIN is the input and V(5), the voltage at node 5, is the output.
*.TF V(5) VIN
* This does an AC analysis (Input: Vin)
* inputs are swept from 1 hertz to 1 MHz
* by decades with 10 points per decade.
*.AC DEC 10 1 1Meg
* This command does noise calculations.
* Output data trace V(onoise) is the noise spectral voltage density
* .NOISE V(5) VIN DEC 10 1 1Meg
* This command does a transient analysis.
.TRAN 10u
* The following statements describe the circuit to PSpice.
* Uses +15 and -15 volts power supplies
.PARAM VSUPPLY=15
* VIN is the input for this circuit.
* It has an amplitude during AC analysis of 1 volt
* and a pulse waveform as specified
VIN 1 0 AC 1. pulse(-10m 10m 0 10n 10n 2.5u 5u)
VCC 3 0 DC {VSUPPLY}
VEE 4 0 DC {-1*VSUPPLY}
X1 1 2 3 4 5 UA741
R1 1 0 1Meg
R2 2 5 1
* Transient response test circuit, from SGS-Thomson uA741 data sheet:
R3 5 0 2.0k
C1 5 0 100p
.PRINT DC V(1) V(5) V(onoise)
* Subcircuit and model definitions from opamp741.NET
*
.SUBCKT UA741 1 2 3 4 5
* 1=Non-inv i/p, 2=inv i/p, 3=Vcc+, 4=Vcc-, 5=OUT
*
Q1 9 1 10 NPN
Q3 9 2 11 NPN
Q6 14 15 6 NPN
Q7 3 12 15 NPN
Q10 13 16 17 NPN
Q11 16 16 4 NPN
Q5 12 15 7 NPN
Q13 14 19 4 NPN
Q14 20 14 21 NPN
Q16 22 23 20 NPN
Q17 20 21 19 NPN
Q18 22 24 5 NPN
Q19 3 22 24 NPQ
Q2 12 13 10 PNP
Q4 14 13 11 PNP
Q8 9 9 3 PNP
Q9 13 9 3 PNP
Q12 18 18 3 PNP
Q15 22 18 3 PNP
R1 7 4 1k
R2 15 4 50k
R3 6 4 1k
R4 17 4 5k
R5 18 16 39k
R6 22 23 4.5k
R7 23 20 7.5k
R8 21 4 50k
R9 19 4 50
R10 24 5 25
R11 5 25 50
Q21 5 5 23 NPN
Q20 4 20 25 PNQ
C1 14 22 30p
.MODEL NPN NPN BF=160 RB=100 CJS=2P TF=0.3N TR=6N CJE=3P CJC=2P VAF=100
.MODEL NPQ NPN BF=160 RB=100 CJS=2P TF=0.3N TR=6N CJE=3P CJC=2P VAF=100 IS=2P
.MODEL PNP PNP BF=20 RB=20 TF=1N TR=20N CJE=6P CJC=4P VAF=100
.MODEL PNQ PNP BF=20 RB=20 TF=1N TR=20N CJE=6P CJC=4P VAF=100 IS=2P
.ENDS
.END
|
The result from the small-signal transient response simulation is shown below.
The example project file "T12AX7.CCT" contains the circuit for this preamplifier, which includes the relevant SPICE data for export to a SPICE netlist.
This circuit does not include the SPICE model for the valve this time, because
we will be using the SPICE model valve library obtainable in a file Tubemods.zip from:
Norman Koren - Vacuum tube audio page (http://www.normankoren.com/Audio/)
The essential netlist lines exported from Circuit Scribe comprise the following in the netlist
file passed to Linear Technology Corporation's SwitcherCAD 3 software:
C1 3 0 0.68u R4 6 5 100K R1 1 0 1Meg R3 3 0 2.7k R2 1 4 68k * V1 4 5 3 0 2 12AX7 ; pinouts differ and Spice doesn't like "V" name X1 5 4 3 12AX7 |
Note that because of the extra pinouts in the Circuit Scribe valve for the heater pins, the line for the valve was changed to omit the heater pins and present the nets in the expected order (anode, grid, cathode). The valve label was also changed from V1 to X1 because SPICE voltage generator elements start with 'V'. Resistors in the Megohm region are common in valve circuits, and their units must be written as "Meg" for SPICE netlists.
In this example, the SPICE netlist saved from Circuit Scribe is the main netlist. Additional
elements were added to include the following essentials:
*SPICE Triode preamplifier * VIN is the input for this circuit. * 1.5 V peak gives a THD of about 16%. VIN 1 0 SINE(0 1.5 1.0K) * The power supply V1 6 0 DC 250 ; Anode supply C1 3 0 0.68u R4 6 5 100K R1 1 0 1Meg R3 3 0 2.7k R2 1 4 68k * V1 4 5 3 0 2 12AX7 ; pinouts differ and Spice doesn't like "V" name X1 5 4 3 12AX7 * Transient analysis .tran 5m * From the valve models at http://www.normankoren.com/Audio/ * Norman Koren - Vacuum tube audio page * .lib C:\LAYIN\Spice models valve\tube.lib .options maxstep=10u .fourier 1K V(5) * To see the output of a .four statement, select View - Spice Error Log .end |
The result from a 1.5V peak sine wave input is shown below.
The SwitcherCAD simulation also gives us a Fourier transform output with the total harmonic distortion calculated as 16.05%.
Objects that are not relevant to a netlist should be excluded, by right-clicking on the object, selecting "Edit object's settings and properties", and under the "Object settings" tab checking the "Exclude from netlist" checkbox. This is useful to exclude symbols that have no corrresponding element in a PCB layout, for example a ground symbol. It is usually more convenient to have the "Exclude from netlist" property set up in a library part.
The example project file "BJTAmp.cct" contains a bipolar transistor amplifier circuit containing the relevant data for exporting a PCB netlist.
The BJTAmp example will produce the following PCB netlist:
Gnd C2-1 R2-1 R3-1 C4-1 1 C1-2 Q1-b R1-1 R2-2 2 C3-1 Q1-c R4-1 Vcc R1-2 R4-2 C4-2 4 C3-2 P2-1 5 C1-1 P1-1 6 C2-2 Q1-e R3-2 END |
Links
http://bach.ece.jhu.edu/~haceaton/pcb/
http://pcb.sourceforge.net/
Link:
http://www.freepcb.com/
An example of PADS-PCB format is shown below (exported from sample project file "BJTAmp.cct").
*PADS-PCB* *PART* C1 RAD-197 C3 RAD-197 C2 RAD-315 Q1 TO-18 P2 TP-1S-M P1 TP-1S-M R1 RC05 R4 RC05 R2 RC05 R3 RC05 C4 RAD-315 *NET* *SIGNAL* Gnd C2.1 R2.1 R3.1 C4.1 *SIGNAL* N00001 C1.2 Q1.b R1.1 R2.2 *SIGNAL* N00002 C3.1 Q1.c R4.1 *SIGNAL* Vcc R1.2 R4.2 C4.2 *SIGNAL* N00004 C3.2 P2.1 *SIGNAL* N00005 C1.1 P1.1 *SIGNAL* N00006 C2.2 Q1.e R3.2 *END* |
If you are exporting to both SPICE and PCB programs, it may not be possible to have pin names that satisfy the requirements of both.
For example, the TO-18 package in FreePCB requires the pin names "c", "b", and "e" changed to "1", "2" and "3".
The following screen shot shows the result after importing the PADS-PCB file into FreePCB. The component packages are shown lined up on the left ready for placement, and I have selected and moved the transistor (specified as a TO-18 through-hole can type) to the centre of the screen.
